"Watson A.Name - \"Watt Sun, the Dark Remover\"" wrote:

Opinions on this, especially the 2.5W amp schem at the bottom.
http://www.intio.or.jp/jf10zl/EF.htm

When the amp is idle, and there's no(?) current flowing in either output
transistor because there's no forward bias, then the V drop 'resistance'
of the E-B junction adds to the 100k feedback resistor, so the loop gain
increases to the open loop gain. So it would seem that the amp would
attempt to hunt in this region, possibly oscillating?

Maybe a 1k resistor E to B on the output transistors would 'bypass'
this. Or should the amp be biased to work class AB.

Start with the "obvious" DC initial conditions: pins 5 and 6 are at
1/2 of the supply voltage.
Note average DC current thru R4 must be exactly zero (am assuming zero
input bias current in op amps and zero leakage current for C6 and C7).
Then pins 7, 9, 10, 12 and 13 are all within an op-amp Vos of 1/2 of
the supply voltage.
Now we see the dicey part; theoretically (acting seperately), opamp C
will drive Q1 until the inputs "see" its Vos, and opamp D would drive Q2
until the inputs "see" its Vos.
Housesomever, zee soykut iss a mess.
The input conditions that opamp C will try to satisfy is virtually
*guaranteed* to be different than the input conditions that opamp D will
try to satisfy (the Vos of one will be different than the Vos of the
other).
Ignoring that feedback, the conclusion seems to be that the opamp with
the greater open loop power gain (that includes the transistor) will
(mostly) win, meaning the other transistor will either be driven to
saturation or zener E-B breakdown.
But, remember that no DC current can flow thru R4.
It *does* appear that your supposition of oscillation is correct.
Now, replace the transistors with E-to-B resistors and one still has
the problem.
Zhoe, vee zee zhat zee soykut iss a mess.
sCRAP.